This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-187053, filed Jun. 30, 1999; and No. 11-263742, filed Sep. 17, 1999, the entire contents of which are incorporated herein by reference.
Integral parts of recent computers and communication equipment often comprise large-scale integrated circuits (LSI) formed by electrically connecting a large number of transistors, resistors, and the like together so as to form an electric circuit and integrating the circuit on one chip. Thus, the performance of the entire equipment heavily depends on the performance of the unitary LSI. The performance of the unitary LSI can be improved by increasing the degree of integration, that is, reducing the size of elements.
For example, in MOS transistors, the size of elements can be reduced by reducing gate length and the thickness of a source/drain diffusion layer(region).
The low-acceleration ion implantation method is widely used to form a shallow source/drain diffusion layer. This method enables formation of a shallow source/drain diffusion layer of thickness 0.1 xcexcm or less.
Since, however, the source/drain diffusion layer formed by the low-acceleration ion implantation method has a high sheet resistance of 100xcexa9 or more, elements simply having their thickness reduced in this manner are not expected to operate at an increased speed.
Thus, devices such as logic LSIs which require high speeds employ the salicide technique of forming a silicide film on a surface of the source/drain diffusion layer and a surface of a gate electrode (a polycrystalline silicon film doped with impurities) in a self-alignment manner.
To form a dual-gate MOS transistor (an n-channel MOS transistor and a p-channel MOS transistor formed on the same substrate wherein a gate electrode of the n-channel MOS transistor comprises a polycrystalline silicon film doped with n-type impurities and a gate electrode of the p-channel MOS transistor comprises a polycrystalline silicon film doped with p-type impurities), the salicide technique can reduce not only the resistance of the gate electrodes but also the number of required steps.
This is because the gate electrodes (the polycrystalline silicon films) can be doped with impurities of a predetermined conductivity type in an ion implantation step for forming the source/drain diffusion layer.
On the contrary, to form a dual-gate MOS transistor employing a structure having a metal silicide film such as a W silicide film laminated on a polycrystalline silicon film doped with polycide impurities, the polycrystalline silicon film is masked with the metal silicide film in the ion implantation step for forming the source/drain diffusion layer, so that the polycrystalline silicon film cannot be doped with impurities of a predetermined conductivity type.
Accordingly, the polycrystalline silicon film must be doped with impurities of a predetermined conductivity type before formation of the source/drain diffusion layer. That is, separates ion implantation steps are required to form the source/drain diffusion layer and to dope the polycrystalline silicon film with impurities of a predetermined conductivity type, thereby increasing the number of required steps.
Specifically, this method requires two more photolithography steps, two more ion implantation steps, and two more resist removal steps than the salicide technique.
On the other hand, in devices such as memory LSIs in DRAMs or the like which require elements to be densely integrated and formed, a SAC (Self-Aligned Contact) structure is essential.
One of processes for forming the SAC structure etches an interlayer insulating film on one side of the source/drain diffusion layer (that is typically used as a source) by means of the RIE (Reactive Ion Etching) method to form contact holes for the source/drain diffusion layer.
In this case, a surface of the gate electrode (the polycrystalline silicon film) must be prevented from being exposed even if the contact holes are misaligned. To achieve this, a silicon nitride film is formed on the gate electrode as an etching stopper film in advance.
Such a silicon nitride film precludes impurities from being injected into the gate electrode in the ion implantation step for forming the source/drain diffusion layer. Consequently, the memory LSIs reject the salicide technique, as used for the logic LSIs.
The memory LSIs conventionally commonly use a gate electrode (a polycrystalline silicon gate electrode) comprising a polycrystalline silicon film doped with impurities and also use a polycide gate electrode due to the need to reduce resistance.
If a gate electrode having a lower resistance is required, a polymetal gate electrode is used which is formed by sequentially laminating a polycrystalline silicon film doped with impurities, a barrier metal film, and a metal film such as a W films. Since the polymetal has a lower resistance than the polycide gate electrode, it achieves a desired sheet resistance with a smaller thickness.
The polymetal gate electrode, however, has the following problems: The logic LSIs use the above described dual-gate structure. Thus, if the logic LSI uses the polymetal gate electrode, separate steps are required to ion-inject impurities into a polycrystal-line silicon film of the polymetal gate electrode and to ion-inject impurities into a silicon substrate to form the source/drain diffusion layer, as with the polycide gate electrode, thereby increasing the number of required steps and thus manufacturing costs.
In an LSI with logic ICs and DRAMs mixed together, if the silicide film is formed on the surface of the source/drain diffusion layer, a pn junction leak current from memory cells increases to prevent retention of data. In addition, the DRAM uses a W polycide electrode because of the needs for the SAC structure as described above.
On the other hand, the logic LSI must have a low threshold voltage for the MOS transistors in order to maximize current at a low voltage. Thus, the polycrystalline silicon film of the gate electrode of the n-channel MOS transistor is doped with n-type impurities such as P or As so as to be formed into an nxe2x88x92type, while the polycrystalline silicon film of the gate electrode of the p-channel MOS transistor is doped with p-type impurities such as BF2 so as to be formed into a p+ type.
To improve the performance of the transistor, it is insufficient to simply reduce the resistances of the source, drain, and gate, and reducing variations in transistor characteristics is very important. One of the major causes of the variations in characteristics is variations in threshold voltage.
Next to variations in processing dimensions, the shape of an element-isolating insulating film at ends of element regions has the largest effect on the variances in threshold voltage. For highly integrated circuits with elements separated mutually by about 0.3 xcexcm or less, STI (Shallow Trench Isolation) is commonly used; that is, trenches (element isolating grooves) are formed to a depth of 0.2 to 0.3 xcexcm, the CVD method is subsequently used to deposit an oxide film all over a surface of a substrate in such a manner as to embed the oxide film in the trenches, and chemical mechanism polishing (CMP) is then used to remove unwanted portions of the oxide film outside each of the trenches in order to isolate the elements.
A TEOS/ozone-based CVD-SiO2 film is conventionally used for the embedding. If trenches (element isolating grooves) formed in a silicon substrate 91 have an aspect ratio between about 1 and 1.5, an oxide film 92 can be embedded in the trenches without creating voids.
If, however, the aspect ratio of the trenches is larger than 1.5 due to the reduced size of the elements, it becomes difficult to embed the oxide film in the trenches without a gap. Voids 93 may be created in the middle of the oxide film, resulting in an incomplete embedded shape, as shown in FIG. 20B.
When the voids 93 are formed, moisture is likely to be absorbed in these gaps to facilitate humidification, thereby degrading the element characteristics. Furthermore, formation of the voids 93 and the level of humidification may vary, so that the voids 93 may vary the element characteristics.
To solve this problem, an embedding method using HDP plasma TEOS has been proposed. With the aspect ratio beyond 2 to 2.5, however, the oxide film has an incomplete embedded shape, also resulting in the voids 93 as shown in FIG. 20B.
When the oxide film 92 is formed while the deposited oxide film is being etched under the application of a substrate bias, the oxide film 92 has an appropriate embedded shape but crystal defects 94 may occur in portions of the substrate surface corresponding to bottoms of the trenches as shown in FIG. 21, thereby degrading the element characteristics. Furthermore, the level of the crystal defects 94 varies, so that the crystal defects 94 varies the element characteristics.
In the STI described in FIGS. 20A and 20B and FIG. 21, the oxide film (the deposited insulating film) 92 is etched at a high rate, so that during a plurality of wet etching steps in an LSI manufacturing process which use a diluted hydrofluoric acid or a diluted ammon fluoride, divots 95 may be formed at upper edges of the trenches as shown in FIG. 22.
In this case, the gate electrode may cut into each of the divots 95 to form at this position a transistor having an apparently low threshold voltage (a corner transistor). Since the depth and shape of the divot 95 have a pattern dependency, the threshold voltage of the corner transistor vary significantly with gate width to vary the threshold voltage of the original MOS transistor. Furthermore, the corner transistor may cause humps as shown in FIG. 23, thereby degrading the element characteristics. Additionally, the depth and shape of the divots 95 are not uniform within a wafer surface, thereby further increasing the variations in element characteristics.
To solve this problem, a thermal oxide film 96 is disposed in an interface between the element region and the element isolating region as shown in FIG. 24. The thermal oxide film 96 reduces the variations, but due to the high rate at which the oxide film 92 is etched, the oxide film 92 and the oxide film 96 recede at a top of the trench as shown in FIG. 24, thereby disadvantageously varying the threshold voltage.
In addition, as shown in FIG. 25, a method has been proposed which first forms the oxide film 92 on the silicon substrate 91 and then uses etching to remove regions of the oxide film 92 corresponding to the element regions, followed by epitaxial growth using as a seed portions of a substrate surface (Si) exposed by means of the etching, to selectively grow a silicon layer 97 in the element regions. This method, however, may form facets 98 (oblique crystal faces), into which the gate electrode may cut, resulting in a problem similar to that with the structure with the divots 95 shown in FIG. 22.
Since loads such as wiring increase consistently with the degree of integration of the LSIs, a current driving capability of the MIS transistor is desirably improved. To improve the current driving capability, the channel length L of the MIS transistor may be reduced or the channel width W thereof may be increased.
To reduce the channel length, an advanced lithography technique, a low-acceleration ion implantation technique, a highly controlled impurity activation technique, or the like must be developed, and high costs are required for such development. In addition, if the channel width is increased, the region occupied by the transistor increases to augment the chip region.
As described above, due to the increased degree of integration of the LSIs, the current driving capability of the MIS transistor is desirably improved, but advanced techniques must be developed to reduce the channel length of the transistor. Disadvantageously, if the channel length of the transistor is increased, the region occupied by the transistor increases.
As described above, the element isolation called the xe2x80x9cSTIxe2x80x9d is carried out for the highly integrated circuits, but when the aspect ratio of the trenches (the element isolating grooves) increases linearly with the size of the elements, it becomes difficult to form an insulating film in the trenches so as to have an appropriate embedded shape, thereby disadvantageously varying the element characteristics.
The present invention is provided in view of the above circumstances, and it is an object thereof to provide a method for manufacturing a semiconductor device that can restrain variations in element characteristics and that enables elements to isolated using the STI. It is another object of the present invention to provide a semiconductor device having MOS type elements and which restrains variations in element characteristics.
To attain these objects, a method for manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a semiconductor substrate, forming openings in the insulating film to partly expose a surface of the semiconductor substrate, using the exposed portion as a seed to epitaxially grow and form a semiconductor layer of thickness sufficient to fill the openings and to extend upward above the insulating film, and removing portions of the semiconductor layer outside the openings.
Another method for manufacturing a semiconductor device according to the present invention comprises the steps of forming a monocrystalline insulating film on a semiconductor substrate, forming a non-monocrystalline insulating film on the monocrystalline insulating film, forming openings in the non-monocrystalline insulating film to partly expose a surface of the semiconductor substrate, using the exposed portion as a seed to epitaxially grow and form a semiconductor layer of thickness sufficient to fill the openings and to extend upward above the insulating film, and removing portions of the semiconductor layer outside the openings.
According to this method for manufacturing a semiconductor device, the epitaxial growth is used to fill the openings with the semiconductor layer, thereby preventing creation of voids, which may cause variations. Furthermore, the semiconductor layer is formed to extend upward from the openings above the insulation film, thereby preventing formation of facets, which may vary the element characteristics. Therefore, the STI can be used to isolate the element to restrain the variations in element characteristics.
Yet another method for manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a semiconductor substrate, forming openings in the insulating film to partly expose a surface of the semiconductor substrate, using the exposed portion as a seed to epitaxially grow and form in the openings a semiconductor layer that is not thick enough to reach an opening surface of each of the openings, and heating the semiconductor layer in an inert gas atmosphere.
According to this method for manufacturing a semiconductor device, the openings are filled with the epitaxially grown semiconductor layer, thereby preventing creation of voids, which may cause variations. In this case, since the semiconductor layer has its top surface formed to be lower than the opening surfaces of the openings, facets may be formed. The subsequent heating, however, flattens the surface of the semiconductor layer to eliminate the facets, which may vary the element characteristics. This method thus enables the element to be isolated based on the STI while restraining the variations in element characteristics.
In addition, a semiconductor device according to the present invention comprises a substrate having a semiconductor layer, an element isolating insulating film for partitioning the semiconductor layer into a plurality of element regions, the element isolating insulating film being formed on the substrate so as to penetrate the semiconductor layer and having a top surface projecting upward above a surface of the semiconductor layer, and a MOS type element formed within a corresponding one of the element regions and having a gate insulating film, wherein a difference in height from the substrate between the top surface position of the element isolating insulating film and the top surface position of the semiconductor layer is at least three times as large as the thickness of the gate insulating film.
Another semiconductor device according to the present invention comprises a substrate having a semiconductor layer, an element isolating insulating film for partitioning the semiconductor layer into a plurality of element regions, the element isolating insulating film being formed on the substrate so as to penetrate the semiconductor layer and having a top surface projecting upward above a surface of the semiconductor layer, and a MOS type element formed within a corresponding one of the element regions, wherein a difference in height from the substrate between the top surface position of the semiconductor layer and the top surface position of the element isolating insulating film is at least 10 nm.
When the difference between the top surface position of the element isolating insulating film and the top surface position of the semiconductor layer with the MOS type elements formed thereon (the semiconductor layer in the element regions) as in the semiconductor devices according to the present invention, variations in element characteristics, particularly, variations in threshold voltage can be effectively restrained, as described in detail in the embodiment section.
It is another object of the present invention to provide a semiconductor device including a MIS type transistor and which can enhance a current driving capability with the same channel length.
To attain this object, a semiconductor device according to the present invention comprises a semiconductor substrate having on its surface a recess and at least one projection formed in the recess, the projection having a channel region, an element isolating insulating film formed in the recess, a MIS type semiconductor element formed on the semiconductor substrate and including a gate electrode formed on the channel region of the projection via a gate insulating film, and a source and a drain regions formed to pinch the channel region of the projection therebetween, wherein a channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess, and a top surface of the at least one projection is located higher than the top surface of the element isolating insulating film.
Another semiconductor device according to the present invention comprises a semiconductor substrate having a recess and projections formed on its surface, an element isolating insulating film formed in the recess and having its top surface below top surfaces of the projections, and a MIS type semiconductor element using a region of the semiconductor substrate as a channel region and including a gate electrode formed on the channel region via a gate insulating film, and a source and a drain regions formed to pinch the channel region therebetween, wherein the channel region of the MIS semiconductor element is divided into at least two sections in the channel width direction by means of the element isolating insulating film and has first regions near steps between the recess and the projections and second regions corresponding to the projections between the first regions, and Wixe2x88x92Wt greater than Gt where Gt denotes the sum of the widths of the recess in the channel with direction, Wt denotes the sum of the widths of the projections in the channel with direction, and Wi denotes an assumed channel width of an assumed semiconductor element in which its channel width is equal to that of the MIS type semiconductor element, in which the current density of a current through its channel region is equivalent to that of a current through the second regions of the MIS type semiconductor element, and in which the total current through its channel region is equivalent to that through the channel region of the MIS type semiconductor element.
According to the semiconductor device of the present invention, the channel region is divided by the isolating insulating film having its top surface below the top surfaces of the projections, thereby increasing the current density of a current through the channel region near the steps between the recess and the projections.
By assuming a semiconductor element taking an increase in current near the steps into account and configuring the element so that Wi xe2x88x92Wt  greater than Gt where Wi denotes an assumed channel width of this assumed semiconductor element, Gt denotes the sum of the widths of the recess in the channel with direction, and Wt denotes the sum of the widths of the projections in the channel with direction, the current driving capacity can be enhanced compared to conventional elements, without increasing the region occupied by the element.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.